`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:36:38 11/23/2011 
// Design Name: 
// Module Name:    Filtr 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module filtrDA(
	input signed[7:0] signal,
	output reg signed [8:0] filtered_sig,	
	
	input clk,
	input reset
    );
	
	reg signed[7:0] r0,r1,r2,r3,r4,r5,r6,r7,r8;
	reg signed[23:0] out_sig;
	
	wire signed[16:0] y0,y1,y2,y3,y4,y5,y6,y7;
	wire signed[8:0] x0, x1, x2, x3, x4, x5, x6, x7;
	
	 lut  l0(.table_in(x0), .table_out(y0));
	 lut  l1(.table_in(x1), .table_out(y1));
	 lut  l2(.table_in(x2), .table_out(y2));
	 lut  l3(.table_in(x3), .table_out(y3));
	 lut  l4(.table_in(x4), .table_out(y4));
	 lut  l5(.table_in(x5), .table_out(y5));
	 lut  l6(.table_in(x6), .table_out(y6));
	 lut  l7(.table_in(x7), .table_out(y7));

	
	always@(posedge clk) begin
		if(reset) begin
			r8<=0;
			r7<=0;
			r6<=0;
			r5<=0;
			r4<=0;
			r3<=0;
			r2<=0;
			r1<=0;
			r0<=0;
		end else begin
			r8<=r7;
			r7<=r6;
			r6<=r5;
			r5<=r4;
			r4<=r3;
			r3<=r2;
			r2<=r1;
			r1<=r0;
			r0<=signal;
			
			
			
			
			
			filtered_sig <= out_sig[23:15]; 
		end	
	end
		
	
	assign x0={r8[0],r7[0],r6[0],r5[0],r4[0],r3[0],r2[0],r1[0],r0[0]};
	assign x1={r8[1],r7[1],r6[1],r5[1],r4[1],r3[1],r2[1],r1[1],r0[1]};
	assign x2={r8[2],r7[2],r6[2],r5[2],r4[2],r3[2],r2[2],r1[2],r0[2]};
	assign x3={r8[3],r7[3],r6[3],r5[3],r4[3],r3[3],r2[3],r1[3],r0[3]};
	assign x4={r8[4],r7[4],r6[4],r5[4],r4[4],r3[4],r2[4],r1[4],r0[4]};
	assign x5={r8[5],r7[5],r6[5],r5[5],r4[5],r3[5],r2[5],r1[5],r0[5]};
	assign x6={r8[6],r7[6],r6[6],r5[6],r4[6],r3[6],r2[6],r1[6],r0[6]};
	assign x7={r8[7],r7[7],r6[7],r5[7],r4[7],r3[7],r2[7],r1[7],r0[7]};

	always @(*) begin
	out_sig = y0 + (y1*2) + (y2*4) + (y3*8) + (y4*16) + (y5*32) + (y6*64) + (y7*128);
	end
	
	
	
endmodule
